This invention relates to speculative registers implemented in a programmable processor.
Conventional programmable processors, such as digital signal processors include a variety of hardware designed to improve performance of the processor and increase the speed at which software instructions are executed. The additional hardware, however, typically increases the power consumption of the processor.
“Pipelining” is a technique used in conventional programmable processors in which instructions are overlapped in execution in order to increase overall processing speed. A pipelined processor typically processes instructions in a number of stages. An instruction moves from one stage to the next according to a system clock, which typically has a clock rate determined by the slowest stage in the pipeline.
While processing instructions, “hazards,” sometimes prevent the next instruction in the instruction stream from executing. For example, a data hazard may arise when an instruction depends on the results of a previous instruction that has not finished processing within the pipeline. Only when an instruction has finished being processed within the pipeline are its results written to architectural registers, where the results are generally accessible to subsequent instructions in the pipeline. Data Hazards, therefore, cause the pipeline to “stall” and reduce the pipeline's performance.
One type of hardware addition that may be implemented to improve pipeline throughput and avoid stalls is a speculative register. A speculative register is a register that speculates or predicts the value that the architectural register will have when the processing of an instruction in the pipeline has finished. However, sometimes an instruction that writes to the speculative register is terminated before it writes to the architectural register. In such a case, the speculative register may require adjustment.